This invention generally relates to semiconductor devices, and more particularly to an arrangement for linearizing the channel resistance of a field-effect transistor and thereby improving its utility as a voltage-controlled resistance element.
Certain properties of the field-effect transistor, especially the well known metal-oxide-semiconductor field-effect transistor (MOSFET), make it desirable for use in solid-state circuits as a voltage controlled resistance element. The MOSFET is a voltage-controlled device, in which the resistance between source and drain electrodes may be controlled by the voltage applied to the gate electrode. Typically, the device comprises two relatively highly-doped, spaced-apart regions of one conductivity type formed in the surface of a semiconductor body region of the opposite conductivity type; these two spaced-apart regions are referred to as the source and drain, respectively. A thin layer of insulating material, usually a thermally grown native oxide layer, is formed over the surface of the semiconductor body region between the source and the drain regions to provide the gate dielectric, and a layer of conductive material, such as metal or polycrystalline semiconductor, is formed on the gate dielectric between the source and drain regions to serve as the gate electrode. Individual electrical contacts are made to the source and drain regions to provide source and drain electrodes.
With the body region tied to a reference potential, such as ground, a voltage applied to the gate electrode controls the number of charge carriers in a channel created at the surface of the body region between the source and the drain regions. For example, in a P-channel MOSFET formed in an N-type silicon substrate and having P-type source and drain regions, a negative voltage bias applied to the gate electrode modifies conditions within the surface of the silicon substrate. As the magnitude of this negative voltage bias increases, the silicon surface beneath the gate electrode first undergoes depletion, followed by weak inversion, and then by increasingly strong inversion. When inversion occurs in the silicon surface beneath the gate electrode, a P-type inversion layer, or channel, extends between the P-type source and drain regions of the MOSFET. Thus, an appropriate voltage signal on the gate electrode can modulate the number of carriers within the channel electrode so that for a given voltage across the source and drain electrodes, the gate electrode controls current flowing in the channel. For constant gate voltage, an increase in the voltage across the source and drain electrodes causes an increase in the channel current, which in turn produces an increase in the resistive voltage (IR) drop along the channel. This voltage drop produces an electric field opposing the electric field in the silicon surface produced by the gate bias. When this voltage drop at any point along the channel reaches a value sufficient to reduce the net electric field in the silicon surface to be near the threshold required to cause inversion, "pinch off" of the channel occurs, and the drain current enters "saturation" at a relatively constant value, largely independent of the voltage across the source and drain electrodes of the MOSFET device.
It is the controllability of the channel resistance, which may have a value ranging from megohms to hundreds or tens of ohms depending on its dimensions, applied voltages, and the materials and process used for fabricating the device, that allows the MOSFET device to be employed as a voltage-controlled circuit resistance element. These and other properties of the MOSFET suggest it for numerous applications, such as a solid-state voltage-controlled resistor in equipment, such as variable RC time-constant circuits and voltage-controlled attenuators. However, because the channel resistance, defined as the ratio of the voltage across the channel to the current flowing through the channel, varies with the voltage across the source and drain electrodes, it cannot be used in many applications that require a resistance element which is independent of the direction (or polarity) and magnitude of the voltage across, and current through the element. In short, the value of the controllable resistance of the element should be independent of the voltage applied across the two terminals of the element.
Techniques have been proposed for linearizing the channel resistance of an insulated-gate field-effect transistor. Typically, these are circuit techniques which utilize the transistor in its triode (nonsaturation) region of operation. Several of these techniques are described in an article entitled "Continuous-Time MOSFET-C Filters in VSLI" by Y. Tsividis, M. Banu and J. Khoury, IEEE Transactions, Circuits-Systems, Vol. CAS-33, No. 2, pp. 125-140, Feb. 1986. The circuits described in this article include devices that operate in the manner shown in FIG. 1A or FIG. 1B, which schematically illustrate a MOSFET in its triode (nonsaturation) region of operation having its gate connected to a control voltage V.sub.c. The control voltage V.sub.c may be provided by an automatic tuning system (not shown). The body of the MOSFET is connected to a fixed DC bias V.sub.B. The source and drain voltages, V.sub.S and V.sub.D, are assumed to remain sufficiently low to allow operation in the nonsaturation region. The channel current of the transistor, I, can be written in the form I=i.sub.L -i.sub.N, where i.sub.N is a nonlinear term in V.sub.S and V.sub.D, and i.sub.L is a linear term given by i.sub.L =G(V.sub.D -V.sub.S) with G being the channel conductance. The nonlinearities in the current, I, versus V.sub.S -V.sub.D are mainly second-order, and are cancelled in various ways, for example, by making V.sub.D =-V.sub.S in the arrangement of FIG. 1A, by making V.sub.C an appropriate function of V.sub.S and V.sub.D, or by using pairs of devices connected as in FIG. 1A or 1B and taking the difference of the currents through the two devices while driving the devices in a balanced fashion.
All of the proposed methods described in the aforementioned article suffer from the following limitations:
(a) If the two devices used in a pair are not perfectly matched, the cancellation of the second-order nonlinearities will not be perfect; the same problem occurs if the driving signals used are not perfectly balanced.
(b) The odd-order terms do not cancel out owing to mobility variations caused by variations in the gate field along the channel, and the body effect caused by variations of the substrate field along the channel.
Among the techniques that have been proposed to cancel the odd-order nonlinear terms of the channel current due to the body effect is that described and claimed in U.S. Pat. No. 4,710,726 to Z. Czarnul, and also described in an article entitled "Modification of Banu-Tsividis Continuous-Time Integrator Structure" by Z. Czarnul, IEEE-Transactions on Circuits and Systems, Vol. CAS-33, No. 7, PP. 714-716, Jul. 1986. The Czarnul circuit is a MOS resistive network which employs four matched MOS transistors, each operating in its nonsaturation region. While this circuit cancels nonlinearities caused by the body effect, it does not cancel nonlinearities caused by mobility variation.
An object of the present invention is to provide a highly-linear field-effect transistor voltage-controlled resistance element which overcomes the shortcomings of known techniques for linearizing the channel resistance field-effect transistor device.